Until recently, most fails in CMOS integrated circuits involved behavior that appeared as soon as power was applied. Faulty gates that were supposed to draw no current, for example, drew significant currents. Failure analysis consisted of the physical identification of these gates. Today, there are many more subtle failures. For example, circuits often show good static and low frequency behavior, but produce errors when operated at high frequencies. Other problems stem from proper functionality at some temperatures, and not others, etc. The fails can be as subtle as errors in calculations which occur only when the operating frequency of the chip is above some level. In fact, the performance of modern integrated circuits is verified by operating them at a particular speed, and checking to see if the correct output is produced after a particular set of operations. The process is iterated until a speed is reached where errors appear. The chip is then sold as one that works properly at the highest speed where no errors were detected.
The process of identifying the specific devices or circuits which limit the high speed performance of a chip is commercially critical since the value of the part increases rapidly with increasing computational power. The computational power of a chip is determined by its design and by the frequency at which it operates. However, identification of the devices within a circuit that limit the high frequency performance is difficult today. This is because logic circuits can now involve more than 10 million gates, and the instructions that produce a detectable error in the operation of the microprocessor can involve tens of thousands of cycles of the microprocessor. The detected error can be due to a problem in a single gate during one cycle. Thus, if there are 10 million gates, and the test involves 10 thousand processor cycles, there are potentially 100 billion switching events that must be checked. Existing techniques that involve the serial measurement of the voltage waveforms for every node would be extremely time consuming under such conditions and therefore lack practicality for testing modern integrated circuits.
In the past, dynamic fault imaging has been used in the effort to detect the source of errors in VLSI circuits. Dynamic fault imaging involves IC testers running extensive test patterns and at each test vector, the generation and storage of an e-beam image showing all logic states on a chip. In the past, dynamic fault imaging required hundreds of test vectors to perform such a test; currently, tens of thousands or more are needed due to increased design complexity. This process was done for a good chip and for a failing chip and then digital subtraction of the two data sets was performed to obtain an image of the fault. This method is not widely practiced on modern integrated circuits due to device complexity, multiple metal levels, complex bussing and flip chip packaging, all of which limit the ability of an e-beam based tester to obtain an image in a reasonable amount of time, or at all.
Commonly owned and copending U.S. Pat. No. 5,940,545, entitled NONINVASIVE OPTICAL METHOD FOR MEASURING INTERNAL SWITCHING AND OTHER DYNAMIC PARAMETERS OF CMOS CIRCUITS, incorporated herein by reference, describes a technique referred to herein as picosecond imaging circuit analysis (PICA) which is used to acquire data representing the switching of CMOS gates in an integrated circuit. Every switching event produces a pulse of light which can be captured by an optical detector. In contrast to the previously described e-beam techniques where data must be obtained individually from each net of the circuit, the PICA technique provides a means for obtaining, in a single measurement, the switching waveforms of all of the gates in an integrated circuit. The ability to obtain in a single measurement full switching information from a complex integrated circuit means that the solution for identifying a defect is no longer limited by the length of time required to acquire the relevant data, but rather is limited by the ability to identify a single event in a field of hundreds of billions of switching transitions.